The present invention relates generally to phase locked loop (PLL) circuits, and more particularly to improvements in start-up circuitry for phase locked loops.
In a typical prior art implementation, a PLL circuit (FIG. 1) includes a phase comparator 10 adapted to receive a reference clock input signal and a local clock signal at inputs 11 and 12, respectively. The phases of the two signals are compared and comparator 10 generates either a "too slow" signal (an "up" signal) or a "too fast" signal (a "down" signal) which is applied to the appropriate input 14 or 15, respectively, of a loop filter 16, depending on whether the local clock signal is lagging or leading the reference clock signal. The reference clock signal is also applied as a reference input 13 to the loop filter. The output voltage of the loop filter, which reflects whether the local clock is to be speeded up or slowed down, is applied to an input 18 of a voltage-controlled oscillator (VCO) 19. The loop filter 16 also assists in removing or reducing the higher frequency components and clock jitter otherwise attributable to oscillation of the local clock (about a selected point).
VCO 19 generates an oscillating output signal in the form of a sine wave with a frequency that depends on the output voltage of the loop filter. The output frequency of the VCO signal is adjusted upwardly or downwardly by appropriate adjustment of this control voltage, according to whether the local clock is too slow or too fast, respectively, relative to the reference clock. The VCO output may be supplied as a multiplied clock output 20, and may also subjected be to frequency division by divider 21 before being applied as the local clock signal to the phase comparator 10 on input 12. If the control signal produced by the phase comparator 10 indicates that the local clock is still not synchronized with a selected edge of the reference clock signal, the output frequency of the VCO is fine tuned accordingly, to provide the desired synchronization.
The time interval required for the PLL to lock the local clock in phase alignment with the reference frequency clock signal is the "lock time" or the "start time" or "start-up time" of the PLL. In conventional PLL circuits, lock time has typically run 60 or more milliseconds (msec). During the lock time of a semiconductor PLL chip, the chip is held in reset. A PLL with a highly stable output frequency usually has a very long lock time because correction (through the phase comparator, loop filter and VCO) is achieved in very small increments of upward or downward adjustment of the control voltage. If the lock time is sought to be decreased by using large increments of correction, instability is encountered characterized by undesirable rapid jitter about the proper lock point.
In co-pending application Ser. No. 08/779,907 of J. Chiao et al, commonly assigned herewith ("the '907 application"), a circuit is disclosed by which the lock time interval of the PLL is reduced to a much more manageable level, on the order of only microseconds (.mu.sec). Rapid start-up is particularly desirable for PLL usage in a system that performs a control function, such as in a microcontroller unit. In the circuit of the '907 application, the PLL loop filter uses a preset reference voltage to cause an initial movement of the control voltage level to a value from which it is much more rapidly ramped up to the level necessary to achieve phase locking of the two input signal frequencies.
Thus, when the PLL operation is commenced, the control voltage increases not from an initial point of zero, but from the voltage level of the fixed reference or bias source. Accordingly, it is only necessary to overcome a relatively small voltage difference between the start-up level and the lock level. The reference voltage provides what is tantamount to a dynamic ground, and assures that the PLL will achieve a rapid lock, oscillating upwardly from a threshold voltage level to a point of stabilization at the desired frequency. This objective is attained without penalties of higher processing costs or greater consumption of silicon real estate. Despite this substantial improvement afforded by the circuit of the '907 application, it would be desirable to further reduce lock time.
It is a primary objective of the present invention to provide a PLL circuit that achieves an even faster lock without sacrificing stability.